Characterization of Tunnel Fet for Ultra Low Power Analog Applications

In modern portable devices, the supply voltage is decreased to reduce the power dissipation. However as the supply voltage is scaled down below 0.4V, the normal MOSFET devices cannot be used due to lower ION/ IOFF ratio which will reduce the static power dissipation. Hence for low power applications, Tunnel FET is used as alternatives due to their higher sub threshold swing, extremely low off state current (IOFF) and excellent sub threshold characteristics. Hence Tunnel FET transistor has attracted a lot of attention for analog and RF applications. In Tunnel FET, the dynamic power dissipation will be decreased since the operating voltage is very low (0.4). The power consumption becomes a major bottleneck for further scaling. The continued reduction of MOSFET size is leading to increased leakage current due to short channel effects. A promising alternative for MOSFET which does not suffer from these limitations is Tunneling FET. In this work, characterizing the various parameters of Tunnel FET such as on current, off current, Transconductance generation factor for ultra low power analog applications.